CPO is powered by silicon photonics technology

CPO integrates silicon photonics directly with ASICs to deliver high-bandwidth, low-power optical interconnects for modern AI and data center workloads.

Overview of CPO

Co-Packaged Optics (CPO) is an advanced integration approach where optical engines and silicon photonics components are packaged directly alongside or within the same substrate as switch ASICs or XPUs. This architecture addresses the growing limitations of traditional copper interconnects, including power inefficiency, bandwidth bottlenecks, and signal degradation over distance . By collapsing electrical distances from inches to millimeters, CPO reduces insertion loss, lowers latency, and improves energy efficiency, enabling sub-picojoule per bit performance .

Role of Silicon Photonics

Silicon photonics (SiPh) forms the core of CPO technology. It allows optical transceivers, lasers, and modulators to be fabricated on silicon substrates, enabling high-density, low-power optical links that can scale to hundreds of terabits per second in AI clusters . SiPh integration supports multi-terabit data rates while minimizing the need for high-power DSPs or retimers, which are typically required in pluggable optical modules to compensate for copper interconnect losses .

Benefits of CPO with Silicon Photonics

• Power Efficiency: Reduces energy per bit by shortening electrical paths and minimizing DSP usage .
• Bandwidth Density: Supports extremely high data rates, with 200G/channel becoming mainstream and 800G–1600G transceivers emerging for AI workloads .
• Reduced Latency: Optical engines placed adjacent to ASICs or XPUs minimize signal travel distance, improving real-time data exchange in tightly coupled AI clusters .
• Scalability: Enables large-scale deployment in hyperscale data centers, supporting both scale-up and scale-out architectures .

Packaging Approaches

CPO implementations vary in packaging strategy:

1. Silicon Interposer Approach: Photonic Integrated Circuits (PICs) and Electronic Integrated Circuits (EICs) are co-located on a silicon interposer, providing high-density die-to-die connections but requiring careful thermal management .
2. Organic Substrate Approach: PICs and EICs are stacked or mounted on an organic substrate surrounding the main die, simplifying layout and enabling modular optical engines, as seen in Broadcom and Nvidia designs .

Industry Trends and Adoption

• Broadcom has deployed CPO systems with integrated silicon photonics for Ethernet switches and XPUs, emphasizing low power and high bandwidth .
• Marvell and Nvidia have demonstrated high-speed CPO-enabled AI accelerators with multi-terabit throughput using 3D SiPh engines .
• Market Growth: Sales of lasers and photonic ICs for optical transceivers are projected to grow from $2.4B in 2023 to $5.9B by 2029, driven by AI data center demand .
• Global Competition: China is rapidly scaling domestic silicon photonics capabilities, challenging Western suppliers and accelerating innovation in CPO deployment .

Challenges

• Thermal Management: Co-locating high-power EICs and PICs increases heat density, requiring advanced cooling solutions .
• Interoperability and Serviceability: Fixed optics types in CPO can limit configurability and complicate maintenance .
• Cost and Complexity: High-density packaging and interposer solutions add manufacturing complexity and cost, though they are offset by energy and performance gains .

Conclusion

CPO combined with silicon photonics represents a transformative approach for next-generation data centers and AI infrastructure, offering unmatched bandwidth, energy efficiency, and scalability. By tightly integrating optical engines with processing silicon, CPO overcomes the limitations of copper interconnects and positions silicon photonics as a critical enabler for high-performance computing and AI-driven workloads .